In testing a semiconductor device by a semiconductor test system, the semiconductor device under test is provided with test signals and the resulting output signals of the semiconductor device are compared with expected data to determine whether the semiconductor device functions correctly or not. The repetition rate of the test pattern signals is called a tester rate and is determined by a rate generator circuit. In a modern semiconductor test system, the tester rate dynamically varies in a cycle by cycle basis by a rate generator circuit to properly test a complicated semiconductor device.
FIG. 4 shows a block diagram of a conventional rate generator circuit. The rate generator circuit is formed of a pattern generator 12, a temporary storage 18, a timing generator 11 and a waveform generator 13.
The pattern generator 12 stores rate data for generating a test pattern. The rate data is read out in each clock cycle of a system clock 111 and is sent to the temporary storage 18. The rate data (WDT) is temporarily stored in the temporary storage 18 by a write clock which is synchronized with the system clock 111.
The timing generator 11 reads the rate data (RDT) from the temporary storage 18 with a read clock which is synchronized with the system clock. For each cycle, the timing generator 11 produces a timing pulse and a timing data based on the rate data received from the storage 18. The timing pulse represents a coarse timing indicated by the rate data while the timing data represents a fine timing indicated by the rate data. The coarse timing is a time length which is integer multiple of one cycle of a reference clock in the semiconductor test system and the fine timing is a time length which is shorter than the one cycle of the reference clock.
The waveform generator 13 converts the timing data into a delay time to be added to the timing pulse from the timing generator 11. Thus, the waveform generator 13 generates a test pattern signal by adding the delay time to the timing pulse and by waveforming the timing pulse.
In this rate generator circuit, modernly, the temporary storage 18 has a pipeline structure in which a plural stages of storage such as shift registers (not shown) are series connected to improve a data transfer speed. The rate data (WDT) from the pattern generator 12 is written in the first stage of the registers by the write clock synchronized with the system clock while the rate data (RDT) in the last stage of the registers is read out and transferred to the timing generator 11 by the read clock synchronized with the system clock.
FIG. 5 is a timing chart showing an operation of the rate generator circuit of FIG. 4. In this example, the system clock 111 of FIG. 5A is the same as the timing pulse 113 of FIG. 5C. As noted above, the timing pulse 113 is formed by the coarse timing data designated in the rate data. Although not shown, a reference clock is given to the timing generator whereby the system clock 111 and the timing pulse 113 are generated. For example, the coarse timing in the rate data is an integer multiple of the reference clock. Thus, in each cycle, the time period of the system clock 111, i.e., the timing pulse 113, is determined as an integer multiple of the reference clock based on the rate data given to the timing generator 11.
The write clock 121 of FIG. 5G is generated by the pattern generator in synchronism with the system clock 111 to write the rate data 122 of FIG. 5H in the temporary storage 18. Thus, by the first write clock (1) of FIG. 5G, the rate data AA is stored in the first stage register of the temporary storage 18. The rate data BB, CC, DD . . . are consecutively stored in the temporary storage 18 by the write clock (2), (3), (4) . . . as shown in Figures G and H.
The read clock 112 of FIG. 5E is also synchronized with the system clock 111. The read clock 112 is provided to all the stages of the registers in the temporary storage 18 to shift the rate data to the next stage of register by each read clock 112. Thus, the first data AA is shifted toward the last stage register in the temporary storage 18 every time the read clock 112 is provided. The other rate data BB, CC, DD . . . are also consecutively shifted toward the last stage register.
For example, if the pipeline in the temporary storage 18 has two stages of shift registers as in the case of FIG. 5, by the read clock (3) of FIG. 5E, which is the second clock after the first write clock (1), the rate data 181 of FIG. 5F indicating the data AA is output from the temporary storage 18. The rate data AA is received by the timing generator 11 to form a timing pulse 113 and timing data 114 for the waveform generator 13.
By the read clock (4), the rate data BB is output from the temporary storage 18 and is received by the timing generator 11. In this manner, the rate data stored in the pattern generator 12 is transferred to the timing generator 11 through the temporary storage 18 every time the write clock 121 and the read clock 112 are supplied.
When receiving the rate data, the timing generator 11 distinguishes a coarse timing and a fine timing in the rate data. As noted above, the coarse timing is an integer of the reference clock period while the fine timing is a delay time smaller than one period of the reference clock. Based on the coarse timing, the timing generator 11 generates the timing pulse 113 having time intervals which are integer multiple of the reference clock.
The fine timing is added to the next rate data. In case where the added data carries over the integer of the reference clock, the timing pulse 113 is produced based on the coarse timing, i.e., the integer of the reference clock formed by the addition. The timing pulse 113 is provided to the waveform generator 13. The remainder of the addition, which is smaller than the reference clock period, is transferred to the waveform generator 13 as the timing data 114.
When receiving the timing pulse 113 and the timing data 114, the waveform generator 13 converts the timing data into a delay time and adds the delay time to the timing pulse 113 to generate a test pattern signal of FIG. 5B. In this manner, the test pattern signal having the timing intervals of A, B, C is generated based on the rate data stored in the pattern generator 12.
In the conventional rate generator circuit of FIGS. 4 and 5, the repetition rate of the test pattern signal is limited by the operational speed of the circuit components used in the circuit. For example, a time required for the write cycle to write the rate data from the pattern generator 12 to the temporary storage 18, and a time required for the read cycle to read the rate data from the temporary storage 18 for the timing generator 11 are determined by the operational speed of the circuit components used in the pattern generator, the temporary storage and the timing generator. Therefore, at present, it is considered that the test pattern signal, or a tester rate, of 128 MHz (8 ns period) or higher is difficult to generate in the conventional technology.